ASIC Power Management Architect
Employment Type: Full-Time
Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities Define ASIC power management (architectural and micro-architectural) details, including functions, such as image compute and CPU/GPU, for maximum performance under power and thermal constraints. Perform algorithm development, modeling, and analysis of power management approaches. Identify power optimization techniques applicable at different design levels. Produce detailed documents for proposed implementation or power management block and detailed trade-off analysis for engineering reviews and product roadmap decisions.
Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 5 years of experience in power management or power design/methodology. Experience with ASIC power analysis methodology.
Preferred qualifications: Master's or PhD degree in Electronics, Computer Engineering, or Computer Science, focusing on computer architecture and performance/power analysis. Experience with power components/modeling/trees/distribution network and design. Experience with power design techniques, such as multi-vth/power/voltage domain design, clock gating, power gating, and DVFS/AVS. Experience in droop detection and mitigation, adaptive clock distribution, and aging and process monitors. Knowledge of industry trends, disruptive technologies, and impact of software and architectural design decisions on power and thermal behavior of systems, such as thermal mitigation, scheduling, and cross-layer policy design. Familiarity with PMIC, SMPS, and LDO.
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